1. Field of the Invention
Embodiments of the present invention relate generally to a method of fabricating a semiconductor device. More particularly, embodiments of invention relate to a method of fabricating a semiconductor device using a metal silicide layer to form a contact pad connecting a plurality of stacked conductive layers exposed in a contact hole.
A claim of priority is made to Korean Patent Application No. 2005-0070854, filed Aug. 3, 2005, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of Related Art
As the level of integration in modern semiconductor devices increases, the size and relative spacing of components within the devices tends to decrease accordingly. For example, the channel length of transistors, the active interval, the width of interconnections, the space between interconnections, and the size of contact pads all tend to decrease as the level of integration in a semiconductor device increases.
The process of forming interconnections in a semiconductor device generally includes a step for forming a contact hole and a step for forming an interconnection in the contact hole. As the semiconductor devices become increasingly integrated, the width and horizontal extent of the interconnections tends to decrease and a vertical extent of the interconnections formed within the contact hole tends to increase. Accordingly, an aspect ratio of the interconnections within the contact hole also tends to increase.
In order to increase an operating speed of a semiconductor device and improve a reliability of interconnections formed therein, multi-layered metal interconnections are often used. To form the multi-layered interconnections, a filling technology is generally used to fill a contact hole penetrating a plurality of stacked conductive and insulating layers. A planarization process is then used to planarize an insulating interlayer on top of the stacked conductive and insulating layers. A physical vapor deposition process and/or a chemical vapor deposition process are often used for the filling technology when forming the multi-layered metal interconnections. A metal silicide layer is generally used as a contact pad to connect the multi-layered interconnections stacked in a limited area, thereby forming a low resistance contact.
The metal silicide layer functions as an ohmic layer to provide a low resistance interface between a silicon substrate and a metal layer formed thereon. The metal silicide layer also functions as a diffusion barrier layer to prevent different materials from being diffused between adjacent metal layers in a multi-layered metal system.
The metal silicide layer typically comprises titanium silicide (TiSi2) or a silicide of Group VIII elements such as PtSi2, PdSi2, CoSi2, NiSi2. In a semiconductor device having a size of 0.25 μm or less, titanium silicide or cobalt silicide is generally used.
A method of fabricating a conventional semiconductor device using the metal silicide layer is described below with reference to FIGS. 1A through 1G.
Referring to FIG. 1A, in the conventional method of fabricating a semiconductor device, a first conductive layer 12 is formed with a predetermined thickness on a semiconductor substrate 10. First conductive layer 12 is often formed as an active layer of semiconductor substrate 10 by ion-implanting or diffusing conductive impurities into the surface of semiconductor substrate 10. Alternatively, first conductive layer 12 can be formed as a first gate electrode formed over an active layer formed on semiconductor substrate 10, and insulated from the active layer by a gate insulating layer. Although not shown in the drawings, an isolation layer or a spacer may be formed around first conductive layer 12 to insulate it against electrical influences from adjacent electrical components.
Referring to FIG. 1B, a first insulating interlayer 14 is formed with a predetermined thickness on first conductive layer 12. First insulating interlayer 14 functions to electrically insulate first conductive layer 12 from a subsequently formed second conductive layer 16 shown in FIG. 1C. In addition, first insulating interlayer 14 also functions to facilitate a patterning process performed on second conductive layer 16.
Referring to FIG. 1C, second conductive layer 16 is formed on first insulating interlayer 14. Second conductive layer 16, which is insulated from first conductive layer 12 by insulating interlayer 14, typically acts as an interconnection, or as a second gate electrode of a second transistor formed on first insulating interlayer 14. Second conductive layer 16 typically comprises polysilicon doped with conductive impurities. Although not shown in FIG. 1C, the second transistor typically includes a second active layer formed with a predetermined thickness at one side of the first insulating interlayer 14, a second gate insulating layer formed on the second active layer or on first insulating interlayer 14, and a second gate electrode formed on the second gate insulating layer to be connected to an upper portion of first conductive layer 12.
Referring to FIG. 1D, a second insulating interlayer 18 is formed on second conductive layer 16. Second insulating interlayer 18 is formed with a predetermined thickness to facilitate the formation of a third conductive layer to be formed on second conductive layer 16 and insulated therefrom.
Referring to FIG. 1E, a hard mask layer (not shown) is formed on second insulating interlayer 18, leaving a portion of second insulating interlayer 18 where second conductive layer 16 and first conductive layer 12 overlap exposed. Portions of second insulating interlayer 18, second conductive layer 16, and first insulating interlayer 14 are sequentially removed using the hard mask layer as an etch mask to form a contact hole 20 exposing first conductive layer 12.
Contact hole 20 penetrates second insulating interlayer 18, second conductive layer 16, and first insulating interlayer 14, and exposes a predetermined portion of first conductive layer 12. Contact hole 20 is generally formed using a dry etching method. Preferably, the dry etching method is an anisotropic etching method having excellent etch characteristics in a vertical direction. The anisotropic etching method is performed by flowing a reaction gas to etch second insulating interlayer 18, second conductive layer 16, and first insulating interlayer 14 along a direction perpendicular to semiconductor substrate 10. The anisotropic etching method permits contact hole 20 to be formed relatively well compared to a wet etching method such as an isotropic etching method.
The hard mask layer is etched by the reaction gas during the formation of contact hole 20. For example, contact hole 20 has a vertical section where an opening of second insulating interlayer 18 and an opening of second conductive layer 16 or first insulating interlayer 14 are formed to have substantially the same size. Often, contact hole 20 has an inclined surface at its sidewalls when an opening of second conductive layer 16 or first insulating interlayer 14 is formed smaller than an opening of second insulating interlayer 18.
Referring to FIG. 1F, a third conductive layer 22 comprising a material such as titanium is conformably formed on semiconductor substrate 10 and inside contact hole 20. Third conductive layer 22 reacts at an interface of the first conductive layer 12 exposed by contact hole 20 and second conductive layer 16 to form a metal silicide layer 24. Metal silicide layer 24 is formed by the reaction of the conductive metal having excellent conductivity characteristics and the polysilicon at a high temperature, and functions to decrease a resistance between second conductive layer 16 and a subsequently formed fourth conductive layer 26 (shown in FIG. 1G).
Since a deposition volume ratio of metal silicide layer 24 is significantly higher than that of third conductive layer 22, the inner sidewalls of contact hole 20 where second conductive layer 16 is exposed tend to protrude toward a center portion of contact hole 20 due to metal silicide layer 24.
Referring to FIG. 1G, a fourth conductive layer 26 filling contact hole 20 is formed on semiconductor substrate 10 over third conductive layer 22. Fourth conductive layer 26 electrically connects first conductive layer 12 and second conductive layer 16. Metal silicide layer 24 tends to decrease contact resistance between fourth conductive layer 26 and first conductive layer 12 or second conductive layer 16.
Unfortunately, a cavity 28 may form between first conductive layer 12 and metal silicide layer 24 close to where second conductive layer 16 protrudes toward the center portion of contact hole 20. Since cavity 28 is not filled with fourth conductive layer 26, the electrical characteristics of the semiconductor device are deteriorated.